Thin SiO2/a-Si:H/SiO2 multilayer insulators obtained by electron cyclotron resonance chemical vapor deposition at room temperature for possible application in non-volatile memories

Three-layer MOS structures were patterned by lithography and subjected to a sintering process in forming gas for 20 min. The structures annealed at high temperature present a memory window in their capacitance-voltage dependencies, which means that these structures could have a possible application as gate insulators in non-volatile memory devices. The morphology of the amorphous layers was studied by atomic force microscopy and scanning electron microscopy which revealed increase of the surface roughness and modifications in the a-Si:H layer after the high temperature process.