Line edge roughness induced threshold voltage variability in nano-scale FinFETs

In aggressively scaled devices, the FinFET technology has become more prone to line edge roughness (LER) induced threshold voltage variability. As a result, nano scale FinFET structures face the problem of intrinsic statistical fluctuations in the threshold voltage. This paper describes the all LER induced variability of threshold voltage for 14 nm underlap FinFET using 3-D numerical simulations. It is concluded that percentage threshold voltage (VTH) fluctuations referenced with respect to rectangular FinFET can go up to 8.76%. This work has also investigated the impact of other sources of variability such as random dopant fluctuation, work function variation and oxide thickness variation on threshold voltage.