Tunnel field-effect transistors with germanium/strained-silicon hetero-junctions for low power applications

We have studied a simple structure n-channel tunnel field-effect transistor with a pure-Ge/strained-Si hetero-junction. The device operation was demonstrated for the devices fabricated by combining epitaxially-grown Ge on strained-silicon-on-insulator substrates. Atomic-layer-deposition-Al2O3-based gate stacks were formed with electron cyclotron resonance plasma post oxidation to ensure the high quality metal-oxide-semiconductor interface between the high-k insulator and Ge. While the gate leakage current and drain current saturation are well controlled, relatively higher minimum subthreshold swing of 125 mV/dec and lower ION/IOFF ratio of 103-104 were obtained. It is expected that these device characteristics can be improved by further process optimization.