Quantitative analysis of gate-oxide interface roughening in SiGe/Si virtual substrate-based transistor device structures

Atomic scale roughening of the gate-oxide interface in virtual substrate-based SiGe/Si n-channel metal-oxide-semiconductor field-effect-transistor device structures has been investigated using transmission electron microscopy (TEM). Since the surface of SiGe virtual substrates can be prone to the development of large-scale undulations, the effects of such surface non-planarity on the microstructure of a processed gate-oxide was explored. It was found that the roughness of the interface between the strained Si surface channel and gate-oxide varied significantly (roughness amplitude from 0.2 to 0.6 nm), and correlated with local angular variation of the virtual substrate (VS) surface. These quantitative measurements from electron micrographs were carried out using specially derived computer-based algorithms.